1. Technical Field
This disclosure relates to electronic circuits, and more particularly, the synchronization of operations in memory circuits.
2. Description of the Related Art
Double data rate (DDR) memories have been implemented in computers and other electronic systems over the past decade to increase memory throughput and thus overall system performance. Whereas single data rate (SDR) utilize only a single edge of a clock signal (e.g., the rising edge), a DDR memory utilizes both the rising and falling edges of the clock signal. Accordingly, a DDR memory operating at a given clock frequency may have a throughput that is twice that of an SDR memory operating at the same frequency.
When data is read from a DDR memory, the data (‘DQ’) may be returned with a data strobe signal (‘DQS’) that may be used to indicate the byte boundaries. The DQ signals may be synchronized with the DQS signal when provided by the memory. At the receiving device, the DQS signal may be delayed, with the delay DQS signal being used to capture the incoming DQ signals.
In some DDR memory embodiments, concurrent reads of the memory from multiple channels may be performed. Each channel may include a DLL that is used to delay the DQS signal for that channel. The channel-specific DLL's may be referred to as slave DLL's. An additional master DLL may also be used to determine the amount of delay to be applied to the DQS signal. Indications of the amount of delay determined by the master DLL may be applied to each of the slave DLLs. Each slave DLL may be designed to certain specifications such that the characteristics of each slave DLL are as closely matched to one another as possible. Accordingly, when receiving indications of the amount of delay determined by the master DLL, each slave DLL may apply substantially the same amount of delay. Such an arrangement may allow substantially synchronous transfer of data from a DDR memory on multiple channels.